Electroplating solder Technology is making tin bumps on the chip pads by series processes such as coating, litho, electroplating and etching, and then using high temperature melting the bumps and been packaged, the IC size can significantly be reduced by this technology, and has a high density, low induction, low cost, good heat dissipation and so on. Wafer-level chip scale packaging is generally applicable to large-size solder balls placed on large pads and the solder technology applied in the manufacture of fine pitch and ultra-thin package of the small tin ball way. This technology successfully applied to flip and reflected its superiority.
|Solder Bump Structure||Pl Thickness||UBM Thickness||Other|
Min.Trace Line X Space:10X10UM
1st PI 5um
2nd PI 10um
|RDL:5um Cu UBM:8um Cu+Sn|
Smart Card,VCM Driver,Switch,Audio& Video,EEPROM/Flash/SRAM,MEMS&Sensor,ucontrollers
a. Standard Turnkey process: Min. BG thickness 200um, T/R shipment;
b. Special process: Min. BG thickness 60um, Wafer ring shipment.